1. Field of the Invention
The present disclosure relates to techniques for forming structures on a substrate, and more specifically, to embodiments of an improved double patterning method for forming openings (e.g., vias or trenches) or mesas (e.g., three dimensional bodies, pillars, bars, etc.) on a substrate.
2. Description of the Related Art
As semiconductor device size scaling continues, the ability to form devices or components thereof with small dimensions has become more and more challenging. One solution for achieving high resolution is double patterning. Conventional double patterning involves double exposure and double etch (DPDE) process. That is, a first mask is formed using conventional lithographic patterning techniques followed by a first etch process. Then, a second mask is formed using conventional lithographic patterning techniques followed by a second etch process. Unfortunately, the wafer topography after the first etch processes may negatively impact the formation of the second mask convention due to reduced depth focus and result in overlay errors. Therefore, there is a need in the art for an improved double patterning technique that avoids such wafer topography effects.